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[Embeded-SCM Developverilog-clock

Description: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Platform: | Size: 1024 | Author: 李瑞 | Hits:

[VHDL-FPGA-VerilogVerilog DHL数字钟

Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Platform: | Size: 2048 | Author: 谢树扬 | Hits:

[VHDL-FPGA-Verilogclockv

Description: 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
Platform: | Size: 5120 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilogshzzh

Description: 这是在FPGA上实现的数字钟功能,用VERILOG语言编程,已功过编译,仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
Platform: | Size: 63488 | Author: 吴乔红 | Hits:

[MPIclock

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[VHDL-FPGA-VerilogVerilogHDL_clock

Description: 基于Verilog HDL设计的多功能数字钟,有兴趣的-Verilog HDL-based design of multi-function digital clock, interested
Platform: | Size: 38912 | Author: 沈三思 | Hits:

[Home Personal applicationdigtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序,可以下载至开发板,实现一个智能数字钟功能,计时,校时,闹钟,跑表等功能,也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[VHDL-FPGA-Verilogdigital_clock

Description: 用veriolg写的数字钟实验,具有定点报时,闰年判断,年月日显示,下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Platform: | Size: 1186816 | Author: 屠宁杰 | Hits:

[VHDL-FPGA-Verilogclock_design

Description: 数字钟的verilog代码,quartusII开发环境.-Digital Clock in Verilog code, quartusII development environment.
Platform: | Size: 414720 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilogmultifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码,其功能主要有:时间设置,时间显示,跑表,分频,日期设置,日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilogclock

Description: 本实验实现一个能显示小时,分钟,秒的数字时钟(贝一特电子)Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
Platform: | Size: 1024 | Author: 黄建 | Hits:

[VHDL-FPGA-Verilogverilog

Description: 多功能数字时钟的verilog语言描述,基于quarters II平台-Multifunction digital clock verilog language description of quarters II-based platforms
Platform: | Size: 7168 | Author: lvlv | Hits:

[VHDL-FPGA-Verilogclock

Description: 采用Verilog HDL语言编写的多功能数字钟,包括四个功能:时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Platform: | Size: 3100672 | Author: 陈涵 | Hits:

[VHDL-FPGA-Verilogclock

Description: 多功能数字钟Verilog HDL的源码,能够整点报时,报整点数,设定任意时刻闹钟,低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilogclock

Description: verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Platform: | Size: 1024 | Author: Tuyan | Hits:

[Otherdigitalclock

Description: Verilog数字时钟 实现24小时的监控,用七段码显示出来,包含时序图等 在ISE下仿真-digital clock Verilog
Platform: | Size: 370688 | Author: 唐新明 | Hits:

[VHDL-FPGA-Verilogdigital-clock-

Description: 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
Platform: | Size: 161792 | Author: 西蟀 | Hits:

[VHDL-FPGA-Verilogclock

Description: 用verilog语言实现数字时钟,有注释,规范-Digital clock using verilog language, there are notes, specifications
Platform: | Size: 1024 | Author: messi | Hits:

[VHDL-FPGA-VerilogMultifunction-digital-clock

Description: 这是多功能数字钟的Verilog源程序,此程序已经编译通过,可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Platform: | Size: 493568 | Author: 莫然 | Hits:

[source in ebookDigital-Clock-verilog-

Description: 数字钟的实现,有时分秒,有闹钟模式,通过手动校准时分秒-Digital clock implementations, sometimes every minute, alarm clock mode, manual calibration Minutes
Platform: | Size: 5120 | Author: 王劲松 | Hits:
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